Conservative Symbolic Model-checking of Petri Nets for Speed-independent Circuit Veriication Conservative Symbolic Model-checking of Petri Nets for Speed-independent Circuit Veriication

This paper presents a conservative symbolic model-checking methodology for speed-independent circuits. The circuit speciication is described by using Petri nets, which is the same formalism that several approaches use for synthesis. The technique is based on symbolic BDD-based reachability analysis, modeling both the speciication and the gate-level network behavior by means of boolean functions. To reduce the size of the BDDs representing these functions, the circuit is partitioned into subcircuits. The global state is kept as the implicit product of subcircuit states, thus veriication being conservative, although much more eecient. The applicability of these techniques has been proved by verifying the correctness and speed-independence of some benchmarks.